1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same.
2. Description of the Related Art
The past few decades have witnessed numerous achievements and economically advantageous effects owing to the semiconductor technology scaling. For example, scaling down design rules of a metal oxide semiconductor field effect transistor (MOSFET) enabled a reduced channel length and an increased switching speed. This is because the switching speed becomes faster as the channel length is shorter. However, a short channel length may undesirably result in a short-channel effect, particularly in a p-type device. Therefore, the scaling down of design rules has limitations. The short-channel effect may include, but is not limited to, a change in the threshold voltage (to be abbreviated to TV, hereinafter), excessive drain leakage current, punch through, and drain induced barrier lowering (DIBL).
In addition to the short-channel effect, when semiconductor device regions performing different functions are integrated on a single semiconductor substrate, loading of epitaxial semiconductor layers formed on the respective semiconductor device regions becomes different, so that the epitaxial semiconductor layers formed on the semiconductor substrate may have different heights.